In a high-speed microprocessor and communication systems, a phase locked loop (PLL) is the portion that cannot do without. With the development of the semiconductor industry, operation frequencies of microprocessors have been higher and higher. A PLL is designed in a microprocessor as the system synchronizer as well as the frequency integrator, to eliminate any inconsistence in terms of timing between the external reference clock and internal clock, and to support the need of an internal high frequency clock. The PLL is much needed for system synchronizing, clock or data recovering, and frequency integration, in a communication system. PLL is important in a vast number of applications for system design. Therefore, the PLL has importance in the broad applications of communication systems.
According to a digital PLL broadly used by the industry, FIG. 1 shows the basic circuit structure of the PLL. To a skilled person of this art, the digital PLL 1 is composed of a digital circuit including a phase-frequency detector (PFD) 10, an analogue charge pump 11, a loop filter 12, a voltage controlled oscillator (VCO) 13, and a frequency divider 14. The PFD 10 makes comparison between a feedback signal Fi′ (in which the Fi′ results from a clock signal gone through the frequency divider 14 for frequency dividing) and an external reference signal Fr, and based upon the frequencies and the phase error of the two signals outputs a series of digital increment control signals and decrement control signals to charge/discharge the charge pump 11. The charge pump 11 receives the increment signals and decrement signals from the PFD 10 and converts the input into a control current output. The loop filter 12 receives the control current, filters a high-frequency signal made by the charge pump 11, and generates a control voltage. The combination of the charge pump 11 and the loop filter 12 may convert those digital increment signals and decrement signals from the PFD 10 into an analogue input signal that is acceptable for the VCO 13, to adjust the output frequency as well as phase of the VCO 13. The VCO 13 is an oscillation circuit, based upon the magnitude of the control voltage made by the loop filter for generating a corresponding oscillation frequency.
According to the above, the loop filter 12 in the digital PLL 1 often adopts MIM capacitors capable of differentiating a plurality of high-frequency signals and low-frequency ones.
Unfortunately, referring to FIG. 2 which shows a schematic diagram of a typical MIN capacitor, the thickness d of the dielectric layer in the MIN capacitor 2 between a first metal layer 20 and a second metal layer 22 has to be reduced as the dimensions of MOS components keep being reduced. But such a reduction would end up with reduced capacitor values per unit area and increased capacitor/voltage coefficients
Aiming to the drawbacks of the traditional MIM capacitors, the metal-oxide semiconductor field-effect transistor (MOSFET) has been suggested as a replacement. FIG. 3 shows a simple structure of a MOSFET.
For a digital PLL, a low thickness of the gate oxidation layer in a MOSFET capacitor may result in current leakage if the MOSFET capacitor is adopted in the filter. Such an effect may further result in a phenomenon of phase inconsistence of time clock. It would be a serious threat to the accuracy of the operation of a communication system and consequently make a phase locking process between an output signal from the digital PLL and the reference signal incomplete.
Therefore, according to the issue set forth in previous paragraphs, it is urgently needed to provide a digital PLL capable of compensating the current leakage in the gate oxide layer of the MOS capacitor in the filter, to avoid the incompleteness of the phase locking process.
Besides, the current leakage due to the low thickness of the gate oxide layer would cause jittering that results in poor performance of a PLL, when the MOS capacitor is used for a filter component in the filter circuit.